A semiconductor device such as an IC (integrated circuit) has electronic circuit elements such as transistors, diodes and resistors fabricated integrally on a single body of semiconductor material. Advances in semiconductor materials and processing techniques have resulted in reducing the overall size of the IC circuit elements while increasing their number on a single body. Additional miniaturization is highly desirable for improved IC performance and cost reduction.
Typically, device interconnections in Very Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated (ULSI) semiconductor chips are effected by multilevel interconnect structures containing patterns of metal wiring layers. Wiring structures within a given level are separated by an intralevel dielectric forming horizontal connections between electronic circuit elements, while the individual wiring levels are separated from each other by layers of an interlevel dielectric. Conductive vias are formed in the interlevel dielectric to provide interlevel contacts between the wiring traces and form vertical connections between the electronic circuit elements, resulting in layered connections.
Through their effects on signal propagation delays and performance (e.g., time delay and crosstalk), the materials and layout of these interconnect structures can substantially impact chip speed, and thus IC performance. Signal-propagation delays are due to RC time constants (‘R’ is the resistance of the on-chip wiring, and ‘C’ is the effective capacitance between the signal lines and the surrounding conductors in the multilevel interconnection stack). RC time constants are reduced by lowering the specific resistance of the wiring material, and by using interlevel and intralevel dielectrics (ILDs) with lower dielectric constants k.
In particular, to further reduce the size of devices on ICs, it has become necessary to use conductive materials having low resistivity and to use insulators having a low dielectric constant (e.g., dielectric constant k of less than 4.0) to also reduce the capacitive coupling between adjacent metal lines. A typical metal/dielectric combination for low RC interconnect structures is copper (Cu) with a dielectric such as silicon dioxide SiO2 (dielectric constant of about 4.0).
Methods of manufacturing interconnects having copper containing materials have been developed where copper-containing interconnect structures are typically fabricated by a “damascene” process. In a typical damascene process, metal patterns, which are inset in a layer of dielectric, are formed by the steps of etching holes (for vias) or trenches (for wiring) into the interlevel or intralevel dielectric, optionally lining the holes or trenches with one or more adhesion or diffusion barrier layers, overfilling the holes or trenches with a metal wiring material (e.g., copper) and removing the metal overfill by a planarizing process such as chemical-mechanical polishing (CMP), leaving the metal even with the upper surface of the dielectric. The above-mentioned processing steps are often repeated until the desired number of wiring and via levels have been fabricated.
Fabrication of interconnect structures by damascene processing can be substantially simplified by using a process variation known as “dual damascene,” in which patterned cavities for the wiring level and its underlying via level are filled in with metal in the same deposition step. Dual damascene reduces the number of metal polishing steps by a factor of two, providing substantial cost savings. Dual damascene simply includes forming a trench and an underlying via hole.
Further, in addition to using copper, the use of low k dielectric materials is in heavy demand as they reduce the capacitance between interconnects and improve the switching speed of IC's. When forming vertical and horizontal interconnects by damascene or dual damascene techniques, one or more low k dielectric materials are deposited and pattern etched to form the vertical interconnects (e.g., vias) and horizontal interconnects (e.g., lines).
In back-end-of-line (BEOL) processing, important changes have included the replacement of low-k dielectrics with ultralow-k dielectrics such as air gaps as they have the lowest k value of any material (k value of about 1.0).
Thus, to fulfill future interconnect integration requirements with respect to time delay, cross talk, and power dissipation, and overcome packaging issues, the use of air gaps as the ultimate low-k inter metal dielectric has been widely implemented. As a result, there may be defined specific areas where air gaps must be introduced in the interconnects stack. As shown in FIG. 1, an interconnect stack 10 formed on a silicon substrate 12 may include a high performance area 14 where air cavities must be introduced and areas 16a and 16b which are available for packaging that do not require air cavity introduction.
Typically, as illustrated in FIGS. 2A-2D, integration schemes use a sacrificial material (e.g., Undoped Silicate Glass or USG such as SiO2) 18 deposited at a metal line level 20, a porous material 22 (e.g., a dielectric resin film SiLK™ polymer from Dow Chemical®) and a technique to remove the sacrificial layer, for example, using diluted gaseous or wet HF (Hydrofluoric Fluoride) attack 24 that diffuses through the SILK™ to the USG material (SiLK™ remains unmodified by the process as it is a permeable permanent material). Removal of the sacrificial material 18 results in formation of air cavities 32.
Moreover, in addition to the introduction of a porous insulating material 22 (e.g., SiLK™) and a dense dielectric 18 (e.g., USG) as examples of materials for providing mechanical stability and generating air cavities (air gaps) in-between copper metal lines, the integration of a hard mask 26 on top of the stack 10 to precisely define the region 14 of the stack where air gaps must be introduced has been proposed.
However, when the porous material 22 exhibits a fast diffusion of HF 24 in the lateral dimension of the stack (FIG. 2B), in the bulk of the SiLK™ (as shown by arrow 28) or at the interface SiLK™/USG (arrow 30), it becomes more difficult to control the lateral distribution of air cavities 32 within the stack 10 using such conventional approaches for long HF dips. The disastrous results are thus illustrated in FIGS. 2C-2D; the air cavities extend in the lateral directions beyond the defined region 14 (FIG. 2C) and may even replace all the sacrificial layers 18 (FIG. 2D).
Therefore, there is a need for developing a new and improved method in which air gaps can be formed in an interconnect that addresses the above mentioned problem.